Thursday, March 19, 2020

Free Essays on Global Wind Patterens

Wind Power â€Å"They’re farming a different crop in Wyoming County these days- the wind. Atop a hill in this little town – population 729 – are 10 windmills that are expected to produce enough electricity each year to provide power for 1,700 homes. It’s not hard to see what this piece of the future looks like.† (Ploetz, A1) Wind power was developed as a major alternative energy source during the 1970’s. The interest in finding alternative energy sources has grown tremendously as people are beginning to realize that they are depleting the Earth of irreplaceable natural resources. The technology is now the fastest-growing energy source in the world. The wind turbine, also called a windmill, is a means of harnessing the kinetic energy of the wind and converting it into electrical energy. This is accomplished by turning blades called aerofoils, which drive a shaft, which drive a motor (turbine) and are connected to a generator. This energy is then supplied to a multitude of homes, businesses, factories, etc. The worldwide total wind capacity is 13,400 MW and the year 2000 is expected to significantly increase this amount, according to the trend in recent records of the American Wind Energy Association (AWEA). Wind generating capacity has grown from 2,000 MW in 1990 to the present capacity of more than 3,600 MW. It is predicted that worldwide energy supply may consist of 10% wind power by 2020, with Europe alone producing more than 100,000 MW. â€Å"Global investment in wind turbines should surpass $200 billion by 2010 as part of a rapid growth in investment in renewable energy sources worldwide,† according to Michael Kujawa, senior Allied Business Intelligence Incorporated (Chambers, 14-16) Presently, Europe is far more advanced than the U.S. in its development and implementation of wind power. However, NASA is using the largest, most expensive wind tunnel yet created to test a huge, high-tech wind tur... Free Essays on Global Wind Patterens Free Essays on Global Wind Patterens Wind Power â€Å"They’re farming a different crop in Wyoming County these days- the wind. Atop a hill in this little town – population 729 – are 10 windmills that are expected to produce enough electricity each year to provide power for 1,700 homes. It’s not hard to see what this piece of the future looks like.† (Ploetz, A1) Wind power was developed as a major alternative energy source during the 1970’s. The interest in finding alternative energy sources has grown tremendously as people are beginning to realize that they are depleting the Earth of irreplaceable natural resources. The technology is now the fastest-growing energy source in the world. The wind turbine, also called a windmill, is a means of harnessing the kinetic energy of the wind and converting it into electrical energy. This is accomplished by turning blades called aerofoils, which drive a shaft, which drive a motor (turbine) and are connected to a generator. This energy is then supplied to a multitude of homes, businesses, factories, etc. The worldwide total wind capacity is 13,400 MW and the year 2000 is expected to significantly increase this amount, according to the trend in recent records of the American Wind Energy Association (AWEA). Wind generating capacity has grown from 2,000 MW in 1990 to the present capacity of more than 3,600 MW. It is predicted that worldwide energy supply may consist of 10% wind power by 2020, with Europe alone producing more than 100,000 MW. â€Å"Global investment in wind turbines should surpass $200 billion by 2010 as part of a rapid growth in investment in renewable energy sources worldwide,† according to Michael Kujawa, senior Allied Business Intelligence Incorporated (Chambers, 14-16) Presently, Europe is far more advanced than the U.S. in its development and implementation of wind power. However, NASA is using the largest, most expensive wind tunnel yet created to test a huge, high-tech wind tur...

Tuesday, March 3, 2020

How to Get Writing a Novel off your Bucket List

How to Get Writing a Novel off your Bucket List How to Get â€Å"Writing a Novel† off Your Bucket List Natalie Barelli harbored a dream that's all too familiar for our readers - writing a novel. An IT professional writing a psychological thriller might have seemed like a  pipe dream, but persistence led to a book which by all accounts is a real page-turner. If "writing a novel" is still on your bucket list, you'll find some good inspiration and advice below!Edit:  Just 6 months  after publishing "Until I Met Her", Natalie Barelli got signed by Amazon Publishing's imprint Thomas Mercer. You can read about how that happened here.It was a conversation about bucket lists that got me started. Over a glass of wine - or ten, let’s be honest - my friend and I were lamenting the fact that it’s so easy to put something into the bucket list, but almost impossible to get it out again.So we decided to pick one each, and get on with it. And mine was to write a novel. More specifically, a psychological suspense novel, because I love them. I read them all the time, I am addict ed to them, and find them to be great stories. Ironically, I didn’t use to enjoy writing very much, but I have always loved stories, and the idea of them. And of course probably like anyone who has ever wanted to write a novel, I thought I could write one because I love reading them.Having decided that I would write a novel, I figured there must be structures out there that I could follow, something akin to the three-act paradigm that is used in film narratives. I was hoping for a â€Å"join the dots† style model, something along the lines of â€Å"kill someone in chapter 1† and â€Å"throw in a suspect in chapter 3† then link ‘em up in chapter 2. I got one item out of my bucket list, my house has never been so clean, and I published Until I Met Her on Amazon on 16 June, ten days ago at the time of writing this. To date the novel has received seven five-star reviews, all of which point to a good plot and good writing.I sure didn’t get those on my own.Until I Met Her here is now available on  Amazon, so make sure to get your copy!How close are you to finishing your first novel? Does  Natalie's story sound like a day out of your life?  Please  share your thoughts and experiences, or any question for Natalie, in the comments below!

Saturday, February 15, 2020

Holocaust Essay Example | Topics and Well Written Essays - 750 words - 4

Holocaust - Essay Example The functionality of a family relies on the efforts and contribution of all persons who constitute a given family unit. Clara’s family is no exception in terms of its setting and functionality. The interdependence between members of Clara’s family and other families in the Zolkiew community shows the extent to which families can go in order to remain together and united as one. Family ties were critical to account for during the Nazis occupation in Zolkiew, Poland. Family completeness is influenced by the manner in which family members relate. Clara and her family have close relationship that is characterized by love and care for one another. This factor enhanced the family’s unity during happy and sad times. Given the fact that the Nazis were against the Jews, Clara’s family was a close and direct target. Just like any other Jewish family at the time, Clara’s family was under significant threat. Amid this, the family ties between Clara, her mother, and her father remained close for the purpose of uniting the family. The presence of the Nazis in Zolkiew, Poland jeopardizes the family setting as a safe haven for the Jewish community. Family setups are broken while others are subjected to extreme livelihoods that they were not previously used to. In this respect, there is the aspect of ruined family ties in Clara’s memoir. In fact, she interacted with persons who were direct victims of such experiences. On the same note, the presence of the Nazis in their community could not offer anything short of these experiences. An aspect of help, assistance, and support is depicted by the manner in which Clara’s family relates with the Beck’s. In regard to this experience, it is evident that family ties do not only involve family members, but also friends and families within and without. Insights into the family context are based on strong ties that are established through good relations and

Sunday, February 2, 2020

Questioning the Text Papers Essay Example | Topics and Well Written Essays - 1000 words - 1

Questioning the Text Papers - Essay Example All the three tales interacts to form a coherent picture of the predicaments that the characters face and the possible solutions to the problems. The paper presents a question from the text and discusses it comprehensively with illustrations. Considering the nature of the relationship between characters in the three tales, examine whether the existence of racial ties and commonalities can influence the disposition of an individual toward another person of the same race? Explain the impact of the behavior displayed by characters from similar backgrounds on the efforts to discourage racial discrimination and stereotypes? The text possesses themes of stereotypes and racial prejudice especially towards the Chinese people. It presents several examples that emphasize the idea that the author addresses some of the major problems faced by various victims of racial discrimination. The question emerges from the observations that individual characters who hail from the same ethnic groups, mistreat their fellow counterparts. Instead of providing support for them to thrive and adapt to the harsh systems, they shun them away, and this worsens their situations. There are many scenarios that support the basis of the questions. The relationship between Wei-Chen and Jin is a typical example that illustrates this fact. Another example is the event that transpires between Wong Lai-Tsao and Tze-Yo-Tzuh that was full of betrayal. In brief, the question originates from the negative treatment displayed by various characters to individuals from the same race. The query is significant as it highlights the weaknesses existing in the society between victims of racial prejudice and stereotyping. Research indicates that most individuals in alien countries face discriminations or mistreatment from fellow tribesmen and members of the same race (Shabazz 1238). As minority

Saturday, January 25, 2020

Model for Predicting Fatigue Life of Nanomaterials

Model for Predicting Fatigue Life of Nanomaterials Introduction In the past, the primary function of micro-systems packaging was to provide input/output (I/O) connections to and from integrated circuits (ICs) and to provide interconnection between the components on the system board level while physically supporting the electronic device and protecting the assembly from the environment. In order to increase the functionality and the miniaturization of the current electronic devices, these IC devices have not only incorporated more transistors but have also included more active and passive components on an individual chip. This has resulted in the emerging trend of a new convergent system[1] Currently, there are three main approaches to achieving these convergent systems, namely the system-on-chip (SOC), system-in-package (SIP) and system on package (SOP). SOC seeks to integrate numerous system functions on one silicon chip. However, this approach has numerous fundamental and economical limitations which include high fabrication costs and integration limits on wireless communications, which due to inherent losses of silicon and size restriction. SIP is a 3-D packaging approach, where vertical stacking of multi-chip modules is employed. Since all of the ICs in the stack are still limited to CMOS IC processing, the fundamental integration limitation of the SOC still remains. SOP on the other hand, seeks to achieve a highly integrated microminiaturized system on the package using silicon for transistor integration and package for RF, digital and optical integration[1] IC packaging is one of the key enabling technologies for microprocessor performance. As performance increases, technical challenges increase in the areas of power delivery, heat removal, I/O density and thermo-mechanical reliability. These are the most difficult challenges for improving performance and increasing integration, along with decreasing manufacturing cost. Chip-to-package interconnections in microsystems packages serve as electrical interconnections but often fail by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018 [2]. Lead-based solder materials have been used for interconnections in flip chip technology and the surface mount technology for many decades. The traditional lead-based and lead-free solder bumps will not satisfy the thermal mechanical requirement of these fine pitches interconnects. These electronic packages, even under normal operating conditions, can reach a temperature as high as 150C. Due to differences in the coefficient of thermal expansion of the materials in an IC package, the packages will experience significant thermal strains due to the mismatch, which in turn will cause lead and lead-free solder interconnections to fail prematurely. Aggarwal et al [3] had modeled the stress experienced by chip to package interconnect. In his work, he developed interconnects with a height of 15 to 50 micrometre on different substrate using classic beam theory. Figure 1 shows the schematic of his model and a summary of some of his results. Although compliant intrerconect could reduces the stress experienced by the interconnect, it is still in sufficient. Chng et al. [4] performed a parametric study on the fatigue life of a solder column for a pitch of 100micrometre using a macro-micro approach. In her work, she developed models of a solder column/bump with a pad size of 50micrometre and heights of 50 micrometre to 200 micrometre. Table I shows a summary of some of her results. Table 1.1: Fatigue life estimation of solder column chip thickness (micrometre) 250 640 640 640 board CTE (ppm/K) 18 18 10 5 solder column height (micrometre) Fatigue life estimation/cycle) 50 81 N.A 171 3237 100 150 27 276 3124 150 134 31 518 4405 200 74 38 273 5772 It can be seen from Table 1.1 that the fatigue lives of all solder columns are extremely short. Apart from the 5ppm/K board where there is excellent CTE matching, the largest fatigue life of the solder column is only about 518 cycles. As expected, the fatigue life increases significantly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height increases from 50micrometre to 200micrometre.This is mainly due to the large strain induced by the thermal mismatch as shown in Figure 1.2. The maximum inelastic principal strain was about 0.16 which exceeds the maximum strain that the material can support. Although the fatigue life of the chip to package interconnection can be increases by increasing the interconnects height, it will not be able to meet the high frequency electrical requirements of the future IC where they need to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps, By definition, nanocrystalline materials are materials that have grain size less than 100nm and these materials are not new since nanocrystalline materials have been observed in several naturally-occurring specimens including seashells, bone, and tooth enamel [5, 6]. However, the nanocrystalline materials have been attracting a lot of research interest due to its superior mechanical and electrical properties as compared to the coarse-grained counterpart. For example, the nano-crystalline copper has about 6 times the strength of bulk copper [7]. Furthermore, the improvement in the mechanical properties due to the reduction in grain size has been well-documented. Increase in strength due to the reduction in grain-size is predicted by the Hall-Petch relationship which has also been confirmed numerically by Swygenhoven et al [8] and was first demonstrated experimentally by Weertman [9]. The implantation of nanocrystalline copper as interconnect materials seems to be feasible from the processing viewpoint too. Copper has been used as interconnects materials since 1989 whereas nano-copper has also been widely processed using electroplating and other severe plastic deformation techniques in the past few years. For instance, Lu et al. [10] have reported electroplating of nano-copper with grain size less than 100 nm and electrical conductivity comparable to microcrystalline copper. Furthermore, Aggarwal et al [11] have demonstrated the feasibility of using electrolytic plating processes to deposit nanocrystalline nickel as a back-end wafer compatible process. However, there are certain challenges regarding implantation of nanocrystalline copper as interconnects materials. As discussed above, nanocrystalline copper have a high potential of being used as the next generation interconnect for electronic packaging. However, it is vital to understand their material properties, deformation mechanisms and microstructures stability. Although the increase in strength due to the Hall-Petch relationship which has also been confirmed numerically and experimentally by Weertman [9], the improvement in the fatigue properties is not well documented and no model has been established to predict/characterize these nano materials in interconnection application; conflicting results regarding the fatigue properties have also been reported. Kumar et al [12] reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in tensile stress range and the endurance limit, the crack growth rate also increases. However, Bansal et al. [7] reported that with decreasing grain size, the tensile stress range increases but the crack growth rate decreases substantially at the same cyclic stress intensity range. Thus, nanostructured materials can potentially provide a solution for the reliability of low pitch interconnections. However, the fatigue resistance of nanostructured interconnections needs to be further investigated. Since grain boundaries in polycrystalline material increases the total energy of the system as compare to perfect single crystal, it will resulted in a driving force to reduce the overall grain boundary area by increasing the average grain size. In the case of nanocrystalline materials which have a high volume fraction of grain boundaries, there is a huge driving force for grain to growth and this presented a presents a significant obstacle to the processing and use of nanocrystalline copper for interconnect applications. Millet et al [13] have shown, though a series of systematic molecular dynamics simulations, grain growth in bulk nanocrystalline copper during annealing at constant temperature of 800K can be impeded with dopants segregated in the grain boundaries regions. However, it has been observed that stress can trigger grain growth in nanocrystalline materials [14] and there is no literature available on impeding stress assisted grain growth. There is an impending need to investigate the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growth Dissertation Objectives The goal of present project is to develop a model for the fatigue resistance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the following research objectives are proposed. Develops a model for predicting fatigue life of nanostructured chip-to-package copper interconnections Develops a fundamental understanding on the fatigue behavior of nanocrystalline copper for interconnect application Addresses the issue on the stability of nanocrystalline materials undergoing cyclic loading Overview of the Thesis The thesis is organized so that past research on nanocrystalline materials forms the basis of the understanding and new knowledge discovered in this research. Chapter 2 reviews much of the pertinent literature regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth. Chapter 3 describes a detailed overview of the technical aspects of the molecular dynamics simulation method including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic boundary conditions and neighbor lists. Include in this chapter is the algorithms for creating nanocrystalline materials used in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the long crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical behavior of single and nanocrystalline copper subjected to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growth. Finally, conclusions and recommendations for future work are presented in Chapter 5. Chapter 2 This chapter offers an expanded summary of the literature published with regards to the fabrication methods, characterization, and properties of nanocrystalline materials in addition to a description of existing interconnect technology. 2.1 Off-Chip Interconnect Technologies Chip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 [2]. The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap that semiconductor industry closely follows closely and its projects the need for several technology generations. The package must be capable of meeting these projections in order for it to be successful. This section reviews some of the current interconnect technology. Wire bonding [15] as shown in Figure 2.1, is generally considered as one of the most simple, cost-effective and flexible interconnect technology. The devices on the silicon die are (gold or aluminum) wire bonded to electrically connect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and hence this will not be suitable for high I/O application. Instead of wires in the wire bonding, tape automated bonding (TAB) is an interconnect technology using a prefabricated perforated polyimide film, with copper leads between chip and substrate. The advantage of this technology is the high throughput and the high lead count. However, it is limited by the high initial costs for tooling. An alternative to peripheral interconnect technology is the area-array solution, as shown in Figure 2.3, that access the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is then fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives the highest packaging density methods and best electrical characteristics of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a very demanding technology to establish and operate. With the need for higher I/O density, compliant interconnects have been developed to satisfy the mechanical requirements of high performance micron sized interconnects. The basic idea is to reduce shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their compliant) and hence the name compliant interconnects. Some of recent research in compliant interconnects include Tesseras Wide Area Vertical Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects [17-19] as shown in Figure 2.4. Although compliant interconnects can solve the problem of mechanical reliability issue, they are done at the expense of the electrical performance. Since there is a need to reduce the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in order to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices. Figure 2.4: (a) Wide Area Vertical Expansion, (b) Wire on Wafer and (c) G-Helix [17-19] Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology had demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al [20] had show that nanostructured nickel interconnections, through a Flip Chip test vehicle, was able to improve the mechanical reliability while maintaining the shortest electrical connection length. However, the main disadvantages of this method was the significant signal loss at high frequency signal of nanocrystalline nickel [21]. As discussed above, nanostructure interconnects technology is the most promising interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an alternate materials and a sensible choice of materials in this case would be nanocrystalline copper for its high strength material with superior electrical conductivity. Hence, it would be beneficial to use nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential candidate for nanostructure interconnect. 2.2 Nanocrystalline material Nanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm [22]. Over the past decade , new nanocrystalline or nanostructured materials with key microstructural length scales on the order of a few tens of nanometers has been gaining a lot of interest in the material science research society. This is mainly due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased strength [22] and wear resistance [23]. These unique properties are due to the large volume fraction of atoms at or near the grain boundaries. As a result, these materials have unique properties that are representative of both the grain boundary surface characteristics and the bulk. Recent advances in synthesis and processing methodology for producing nanocrystalline materials such as inert gas condensation [24], mechanical milling [25, 26], electro-deposition [27], and severe plastic deformation [28] have made it possible to produce sufficient nanocrystalline materials for small scale application. 2.2.1 Synthesis Inert gas condensation, the first method used to synthesis bulk nanocrystalline [29], consists of evaporating a metal inside a high-vacuum chamber and then backfilling the chamber with inert gas [30]. These evaporated metal atoms would then collide with the gas atoms, causing them to lose kinetic energy and condenses into powder of small nano-crystals. These powders are then compacted under high pressure and vacuum into nearly fully dense nanocrystalline solids. The grain size distribution obtained from this method is usually very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the compaction stage [31]. Mechanical milling consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a certain percentages of the respective initial constituents [25, 26]. A wide grain size distribution is obtained by this method. This technique is a popular method to prepare nanocrystalline materials because of its applicability to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage. Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital investment requirements and porosity-free finished products without a need for consolidation processing [27]. Furthermore, Shen et al. [32] and Lu et al.[33] had recently show that the right electro-deposition condition can produce a highly twinned structure which leads to enhanced ductility. The main drawback of this method is it is the difficulty to achieve high purity. Severe plastic deformation, such as high-pressure torsion, equal channel angular extrusion (ECAE), continuous confined shear straining and accumulative roll-bonding, uses extreme plastic straining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and geometric re-crystallization [34]. It is the only technology that transformed conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under superimposed hydrostatic pressure. Two of the most commonly used methods are high-pressure torsion and ECAE [35]. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al [36] observed that the grains become more equi-axial and randomly orientation as the number of passes increases, as shown in Figure 2.5 Figure 2.5: Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 passes and (f) 16 passes [36] 2.2.2 Mechanical Behavior of nanocrystalline materials Due to the small grain size and high volume fraction of grain boundaries, nanocrystalline materials exhibit significantly different properties and behavior as compared to their microcrystalline counterpart. The structure and mechanical behavior of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally [37-43] and theoretically [44-50]. This section reviews the principal mechanical properties and behavior of nanocrystalline materials. 2.2.2.1 Strength and ductility Recent studies of nanocrystalline metals have shown that there is a five to ten fold increases in the strength and hardness as compared to their microcrystalline state [7, 36, 37, 51, 52]. This increase in the strength is due to the presence of grain boundaries impeding the nucleation and movement of dislocations. Since decreasing grain boundary size increases the number of barrier and the amount of applied stress necessary to move a dislocation across a grain boundary, this resulted in a much higher yield strength. The inverse relationship between grain size and strength is characterized by the Hall-Petch relationship [53, 54] as shown in equation (2.1). Eq (2.1) In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of hardness and yield strength from tensile test that are reported in the literature. Indeed, hardness and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens. Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sources within the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.[12]. Furthermore, as the grain size reduces, the volume fraction of the grain boundaries and the triple points increases. Material properties will be more representative of the grain boundary activity [64] and this will resulting the strength to be inversely proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation [65]. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the materials soften, will take place. Although sample defects had been account for the earlier experimental observation of reverse Hall-Petch effect[24], Swygenhoven et al [66] and Schiotz et al [47], using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm respectively. Conrad et al [67] pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocation-mediated plasticity and this causes the material to become dependent on strain rate, temperature, Taylor orientation factor and presence of the type of dislocation. The yield stress of nanocrystalline copper was highly sensitive to strain rate even though it is a fcc materials. The strain rate sensitivity, m, in equation 2.2 a engineering parameter which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the literature [51, 68-70]. Due to high localized dislocation activities at the grain boundaries which results in enhanced strain rate sensitivities in nanocrystalline materials, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8. (2.2) Room temperature strain rate sensitivity was found to dependent on dislocation activities and grain boundaries diffusion [52, 71, 72]. Due to the negligible lattice diffusion at room temperature, the rate limiting process for microcrystalline copper was the gliding dislocation to cutting through forest dislocation, resulting in low strain rate sensitivities. However, due to the increasing presence of obstacles such as grain boundaries for nanocrystalline materials, the rate limiting process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al [52] proposed the following model for strain rate sensitivities . (2.3) z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nucleation which led to highly localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was found to be higher than those without any twin boundaries [33]. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been credited for it increases in strength and ductility. For example, Valiev et al [60] credited the enhanced strain rate sensitivity of 0.16 for the high ductility. In addition to a strong dependency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al [73] observed that the yield strength for ultra fine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attributed this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is consistent with Huang et al [74] observation where the temperature dependence of nanocrystalline copper with an increase in hardness of nanocrystalline copper with lowering the temperature is noted Ductility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the presence of grain boundaries acting as effective barriers to the propagation of micro-cracks[75]. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects [76]. Recent advanced in processing of nanocrystalline materials offer materials with fairly good ductility in additional to ultra-high strength. Lu et al [10] reported that nanocrystalline copper with minimal flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al [77] observed a 15.5% elongation to failure for defect free nanocrystalline copper produced via mechanical milling. Hence, it was possible for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized. The failure are usually consists of dimples several time larger than their grain size was normally found on the failure morphology of nanocrystalline materials and Kumar et al [78] presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear localization since the ratio of strain hardening rate to prevailing stress was usually small [79, 80]. Figure 2.9: Schematic illustration of fracture in nanocrystalline material postulated by Kumar et al [78] 2.2.2.2 Creeps Nanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of three as compared to microcrystalline copper [81]. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention. Due to the high volume fraction of grain boundaries and enhanced diffusivity rate Model for Predicting Fatigue Life of Nanomaterials Model for Predicting Fatigue Life of Nanomaterials Introduction In the past, the primary function of micro-systems packaging was to provide input/output (I/O) connections to and from integrated circuits (ICs) and to provide interconnection between the components on the system board level while physically supporting the electronic device and protecting the assembly from the environment. In order to increase the functionality and the miniaturization of the current electronic devices, these IC devices have not only incorporated more transistors but have also included more active and passive components on an individual chip. This has resulted in the emerging trend of a new convergent system[1] Currently, there are three main approaches to achieving these convergent systems, namely the system-on-chip (SOC), system-in-package (SIP) and system on package (SOP). SOC seeks to integrate numerous system functions on one silicon chip. However, this approach has numerous fundamental and economical limitations which include high fabrication costs and integration limits on wireless communications, which due to inherent losses of silicon and size restriction. SIP is a 3-D packaging approach, where vertical stacking of multi-chip modules is employed. Since all of the ICs in the stack are still limited to CMOS IC processing, the fundamental integration limitation of the SOC still remains. SOP on the other hand, seeks to achieve a highly integrated microminiaturized system on the package using silicon for transistor integration and package for RF, digital and optical integration[1] IC packaging is one of the key enabling technologies for microprocessor performance. As performance increases, technical challenges increase in the areas of power delivery, heat removal, I/O density and thermo-mechanical reliability. These are the most difficult challenges for improving performance and increasing integration, along with decreasing manufacturing cost. Chip-to-package interconnections in microsystems packages serve as electrical interconnections but often fail by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018 [2]. Lead-based solder materials have been used for interconnections in flip chip technology and the surface mount technology for many decades. The traditional lead-based and lead-free solder bumps will not satisfy the thermal mechanical requirement of these fine pitches interconnects. These electronic packages, even under normal operating conditions, can reach a temperature as high as 150C. Due to differences in the coefficient of thermal expansion of the materials in an IC package, the packages will experience significant thermal strains due to the mismatch, which in turn will cause lead and lead-free solder interconnections to fail prematurely. Aggarwal et al [3] had modeled the stress experienced by chip to package interconnect. In his work, he developed interconnects with a height of 15 to 50 micrometre on different substrate using classic beam theory. Figure 1 shows the schematic of his model and a summary of some of his results. Although compliant intrerconect could reduces the stress experienced by the interconnect, it is still in sufficient. Chng et al. [4] performed a parametric study on the fatigue life of a solder column for a pitch of 100micrometre using a macro-micro approach. In her work, she developed models of a solder column/bump with a pad size of 50micrometre and heights of 50 micrometre to 200 micrometre. Table I shows a summary of some of her results. Table 1.1: Fatigue life estimation of solder column chip thickness (micrometre) 250 640 640 640 board CTE (ppm/K) 18 18 10 5 solder column height (micrometre) Fatigue life estimation/cycle) 50 81 N.A 171 3237 100 150 27 276 3124 150 134 31 518 4405 200 74 38 273 5772 It can be seen from Table 1.1 that the fatigue lives of all solder columns are extremely short. Apart from the 5ppm/K board where there is excellent CTE matching, the largest fatigue life of the solder column is only about 518 cycles. As expected, the fatigue life increases significantly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height increases from 50micrometre to 200micrometre.This is mainly due to the large strain induced by the thermal mismatch as shown in Figure 1.2. The maximum inelastic principal strain was about 0.16 which exceeds the maximum strain that the material can support. Although the fatigue life of the chip to package interconnection can be increases by increasing the interconnects height, it will not be able to meet the high frequency electrical requirements of the future IC where they need to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps, By definition, nanocrystalline materials are materials that have grain size less than 100nm and these materials are not new since nanocrystalline materials have been observed in several naturally-occurring specimens including seashells, bone, and tooth enamel [5, 6]. However, the nanocrystalline materials have been attracting a lot of research interest due to its superior mechanical and electrical properties as compared to the coarse-grained counterpart. For example, the nano-crystalline copper has about 6 times the strength of bulk copper [7]. Furthermore, the improvement in the mechanical properties due to the reduction in grain size has been well-documented. Increase in strength due to the reduction in grain-size is predicted by the Hall-Petch relationship which has also been confirmed numerically by Swygenhoven et al [8] and was first demonstrated experimentally by Weertman [9]. The implantation of nanocrystalline copper as interconnect materials seems to be feasible from the processing viewpoint too. Copper has been used as interconnects materials since 1989 whereas nano-copper has also been widely processed using electroplating and other severe plastic deformation techniques in the past few years. For instance, Lu et al. [10] have reported electroplating of nano-copper with grain size less than 100 nm and electrical conductivity comparable to microcrystalline copper. Furthermore, Aggarwal et al [11] have demonstrated the feasibility of using electrolytic plating processes to deposit nanocrystalline nickel as a back-end wafer compatible process. However, there are certain challenges regarding implantation of nanocrystalline copper as interconnects materials. As discussed above, nanocrystalline copper have a high potential of being used as the next generation interconnect for electronic packaging. However, it is vital to understand their material properties, deformation mechanisms and microstructures stability. Although the increase in strength due to the Hall-Petch relationship which has also been confirmed numerically and experimentally by Weertman [9], the improvement in the fatigue properties is not well documented and no model has been established to predict/characterize these nano materials in interconnection application; conflicting results regarding the fatigue properties have also been reported. Kumar et al [12] reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in tensile stress range and the endurance limit, the crack growth rate also increases. However, Bansal et al. [7] reported that with decreasing grain size, the tensile stress range increases but the crack growth rate decreases substantially at the same cyclic stress intensity range. Thus, nanostructured materials can potentially provide a solution for the reliability of low pitch interconnections. However, the fatigue resistance of nanostructured interconnections needs to be further investigated. Since grain boundaries in polycrystalline material increases the total energy of the system as compare to perfect single crystal, it will resulted in a driving force to reduce the overall grain boundary area by increasing the average grain size. In the case of nanocrystalline materials which have a high volume fraction of grain boundaries, there is a huge driving force for grain to growth and this presented a presents a significant obstacle to the processing and use of nanocrystalline copper for interconnect applications. Millet et al [13] have shown, though a series of systematic molecular dynamics simulations, grain growth in bulk nanocrystalline copper during annealing at constant temperature of 800K can be impeded with dopants segregated in the grain boundaries regions. However, it has been observed that stress can trigger grain growth in nanocrystalline materials [14] and there is no literature available on impeding stress assisted grain growth. There is an impending need to investigate the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growth Dissertation Objectives The goal of present project is to develop a model for the fatigue resistance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the following research objectives are proposed. Develops a model for predicting fatigue life of nanostructured chip-to-package copper interconnections Develops a fundamental understanding on the fatigue behavior of nanocrystalline copper for interconnect application Addresses the issue on the stability of nanocrystalline materials undergoing cyclic loading Overview of the Thesis The thesis is organized so that past research on nanocrystalline materials forms the basis of the understanding and new knowledge discovered in this research. Chapter 2 reviews much of the pertinent literature regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth. Chapter 3 describes a detailed overview of the technical aspects of the molecular dynamics simulation method including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic boundary conditions and neighbor lists. Include in this chapter is the algorithms for creating nanocrystalline materials used in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the long crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical behavior of single and nanocrystalline copper subjected to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growth. Finally, conclusions and recommendations for future work are presented in Chapter 5. Chapter 2 This chapter offers an expanded summary of the literature published with regards to the fabrication methods, characterization, and properties of nanocrystalline materials in addition to a description of existing interconnect technology. 2.1 Off-Chip Interconnect Technologies Chip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 [2]. The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap that semiconductor industry closely follows closely and its projects the need for several technology generations. The package must be capable of meeting these projections in order for it to be successful. This section reviews some of the current interconnect technology. Wire bonding [15] as shown in Figure 2.1, is generally considered as one of the most simple, cost-effective and flexible interconnect technology. The devices on the silicon die are (gold or aluminum) wire bonded to electrically connect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and hence this will not be suitable for high I/O application. Instead of wires in the wire bonding, tape automated bonding (TAB) is an interconnect technology using a prefabricated perforated polyimide film, with copper leads between chip and substrate. The advantage of this technology is the high throughput and the high lead count. However, it is limited by the high initial costs for tooling. An alternative to peripheral interconnect technology is the area-array solution, as shown in Figure 2.3, that access the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is then fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives the highest packaging density methods and best electrical characteristics of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a very demanding technology to establish and operate. With the need for higher I/O density, compliant interconnects have been developed to satisfy the mechanical requirements of high performance micron sized interconnects. The basic idea is to reduce shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their compliant) and hence the name compliant interconnects. Some of recent research in compliant interconnects include Tesseras Wide Area Vertical Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects [17-19] as shown in Figure 2.4. Although compliant interconnects can solve the problem of mechanical reliability issue, they are done at the expense of the electrical performance. Since there is a need to reduce the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in order to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices. Figure 2.4: (a) Wide Area Vertical Expansion, (b) Wire on Wafer and (c) G-Helix [17-19] Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology had demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al [20] had show that nanostructured nickel interconnections, through a Flip Chip test vehicle, was able to improve the mechanical reliability while maintaining the shortest electrical connection length. However, the main disadvantages of this method was the significant signal loss at high frequency signal of nanocrystalline nickel [21]. As discussed above, nanostructure interconnects technology is the most promising interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an alternate materials and a sensible choice of materials in this case would be nanocrystalline copper for its high strength material with superior electrical conductivity. Hence, it would be beneficial to use nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential candidate for nanostructure interconnect. 2.2 Nanocrystalline material Nanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm [22]. Over the past decade , new nanocrystalline or nanostructured materials with key microstructural length scales on the order of a few tens of nanometers has been gaining a lot of interest in the material science research society. This is mainly due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased strength [22] and wear resistance [23]. These unique properties are due to the large volume fraction of atoms at or near the grain boundaries. As a result, these materials have unique properties that are representative of both the grain boundary surface characteristics and the bulk. Recent advances in synthesis and processing methodology for producing nanocrystalline materials such as inert gas condensation [24], mechanical milling [25, 26], electro-deposition [27], and severe plastic deformation [28] have made it possible to produce sufficient nanocrystalline materials for small scale application. 2.2.1 Synthesis Inert gas condensation, the first method used to synthesis bulk nanocrystalline [29], consists of evaporating a metal inside a high-vacuum chamber and then backfilling the chamber with inert gas [30]. These evaporated metal atoms would then collide with the gas atoms, causing them to lose kinetic energy and condenses into powder of small nano-crystals. These powders are then compacted under high pressure and vacuum into nearly fully dense nanocrystalline solids. The grain size distribution obtained from this method is usually very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the compaction stage [31]. Mechanical milling consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a certain percentages of the respective initial constituents [25, 26]. A wide grain size distribution is obtained by this method. This technique is a popular method to prepare nanocrystalline materials because of its applicability to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage. Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital investment requirements and porosity-free finished products without a need for consolidation processing [27]. Furthermore, Shen et al. [32] and Lu et al.[33] had recently show that the right electro-deposition condition can produce a highly twinned structure which leads to enhanced ductility. The main drawback of this method is it is the difficulty to achieve high purity. Severe plastic deformation, such as high-pressure torsion, equal channel angular extrusion (ECAE), continuous confined shear straining and accumulative roll-bonding, uses extreme plastic straining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and geometric re-crystallization [34]. It is the only technology that transformed conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under superimposed hydrostatic pressure. Two of the most commonly used methods are high-pressure torsion and ECAE [35]. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al [36] observed that the grains become more equi-axial and randomly orientation as the number of passes increases, as shown in Figure 2.5 Figure 2.5: Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 passes and (f) 16 passes [36] 2.2.2 Mechanical Behavior of nanocrystalline materials Due to the small grain size and high volume fraction of grain boundaries, nanocrystalline materials exhibit significantly different properties and behavior as compared to their microcrystalline counterpart. The structure and mechanical behavior of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally [37-43] and theoretically [44-50]. This section reviews the principal mechanical properties and behavior of nanocrystalline materials. 2.2.2.1 Strength and ductility Recent studies of nanocrystalline metals have shown that there is a five to ten fold increases in the strength and hardness as compared to their microcrystalline state [7, 36, 37, 51, 52]. This increase in the strength is due to the presence of grain boundaries impeding the nucleation and movement of dislocations. Since decreasing grain boundary size increases the number of barrier and the amount of applied stress necessary to move a dislocation across a grain boundary, this resulted in a much higher yield strength. The inverse relationship between grain size and strength is characterized by the Hall-Petch relationship [53, 54] as shown in equation (2.1). Eq (2.1) In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of hardness and yield strength from tensile test that are reported in the literature. Indeed, hardness and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens. Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sources within the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.[12]. Furthermore, as the grain size reduces, the volume fraction of the grain boundaries and the triple points increases. Material properties will be more representative of the grain boundary activity [64] and this will resulting the strength to be inversely proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation [65]. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the materials soften, will take place. Although sample defects had been account for the earlier experimental observation of reverse Hall-Petch effect[24], Swygenhoven et al [66] and Schiotz et al [47], using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm respectively. Conrad et al [67] pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocation-mediated plasticity and this causes the material to become dependent on strain rate, temperature, Taylor orientation factor and presence of the type of dislocation. The yield stress of nanocrystalline copper was highly sensitive to strain rate even though it is a fcc materials. The strain rate sensitivity, m, in equation 2.2 a engineering parameter which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the literature [51, 68-70]. Due to high localized dislocation activities at the grain boundaries which results in enhanced strain rate sensitivities in nanocrystalline materials, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8. (2.2) Room temperature strain rate sensitivity was found to dependent on dislocation activities and grain boundaries diffusion [52, 71, 72]. Due to the negligible lattice diffusion at room temperature, the rate limiting process for microcrystalline copper was the gliding dislocation to cutting through forest dislocation, resulting in low strain rate sensitivities. However, due to the increasing presence of obstacles such as grain boundaries for nanocrystalline materials, the rate limiting process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al [52] proposed the following model for strain rate sensitivities . (2.3) z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nucleation which led to highly localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was found to be higher than those without any twin boundaries [33]. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been credited for it increases in strength and ductility. For example, Valiev et al [60] credited the enhanced strain rate sensitivity of 0.16 for the high ductility. In addition to a strong dependency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al [73] observed that the yield strength for ultra fine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attributed this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is consistent with Huang et al [74] observation where the temperature dependence of nanocrystalline copper with an increase in hardness of nanocrystalline copper with lowering the temperature is noted Ductility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the presence of grain boundaries acting as effective barriers to the propagation of micro-cracks[75]. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects [76]. Recent advanced in processing of nanocrystalline materials offer materials with fairly good ductility in additional to ultra-high strength. Lu et al [10] reported that nanocrystalline copper with minimal flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al [77] observed a 15.5% elongation to failure for defect free nanocrystalline copper produced via mechanical milling. Hence, it was possible for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized. The failure are usually consists of dimples several time larger than their grain size was normally found on the failure morphology of nanocrystalline materials and Kumar et al [78] presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear localization since the ratio of strain hardening rate to prevailing stress was usually small [79, 80]. Figure 2.9: Schematic illustration of fracture in nanocrystalline material postulated by Kumar et al [78] 2.2.2.2 Creeps Nanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of three as compared to microcrystalline copper [81]. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention. Due to the high volume fraction of grain boundaries and enhanced diffusivity rate

Friday, January 17, 2020

The Climb (Miley Cyrus)

About two years ago I went on a camping trip to Colorado with youth for Christ. It’s an organization ran through my high school. We all met up at a church and got on a charter bus, that was the longest ride of my life. It was eight-teen hours. It would have been fifteen but our tire popped on the way there. We got it fixed, and kept on moving. The closer we got to the mountains weird things started to happen. Our soda cans and potato chip bags began to pop.We were so high up that the air pressure made everything explode. And the closer we got the better we could see the mountains, because from far away all the mountains looked like hills. But as we got closer you could start to see the snow at the top of them. Which was crazy to me because it was the middle of the summer, but it made me want to get there even faster. So we arrived and people from all over the United States came to camp, so there was a huge crowd of people we didn’t even know waiting to greet us.We all w alked around and got acquainted with almost everyone, then went back to our cabins to unpack and get settled in. After that we had our very first â€Å"lodge meeting†, it was held at this big hall name bear claw. We all sang songs about god and met the camp band named Attaboy. There freaking awesome! Days went by and we all got to know each other a little more. Not all of us got along but we would sure learn to. The night before at dinner they hinted that we would be doing something special, but no one could guess what.They just told us to make sure that we were in our cabins by ten o’clock and to make sure that we had gotten a lot of rest because we would need it. So the next day we woke up and everyone ate a huge breakfast. During breakfast they announced to us that we would be doing things different that day. We all needed to return to our cabins as soon as we finished eating and put on tennis shoes, sun block, to bring a lot of water. After we all did that we met a t the circle and they told us that we were climbing a mountain as a bonding experience.So they put us in groups of three with people in our cabins, but the task was for us to bond with someone that we didn’t know. We started our journey and coincidentally my group had gotten stuck behind a group of girls from Kalamazoo, Michigan. Now none of knew these girls, but I did know that one of them had given me a dirty look at lunch the day before so I wasn’t too thrilled about walking by them. We were all having a nice walk until about half way up the mountain it had gotten really steep.It was like trying to walk up a gravel wall. Everyone on my group successfully made it up, and two people form their group did but for some reason the girl who gave me a dirty look was having trouble. She just couldn’t get up there. Everyone in her group had walked up ahead so I was forced to help her. As I was standing there everything inside of me was telling me not to help her, but I had to think about what if that was me. So I couldn’t jus let her stay down there, so I helped her. We walked up the rest of the mountain together.We talked and I came to find out that she was a really nice person, and she explained to me that she wasn’t giving me a dirty look. She was actually staring at me because she thought that I was really pretty. We walked and talked and finally made it to the top of the mountain. We sat down and ate lunch together and became really close friends, we still keep in touch to this day. So I guess u could say I learned a lesson and experienced the best thing of my life, â€Å"The Climb†. Tiarra Archie Reading 104 August 26,2010

Thursday, January 9, 2020

Why Do We Remember Some Of The Events, But Not All

Why do we remember some of the events, but not all? In today’s society, people tend to have a habit of always being their technology device, where many of the texts status and photos are posted to the media websites. As Horn’s mentions in this short prompt, people instantly want to save or share every moment activities daily in their life. The author also states about people are being fear of death since everybody wants to live for eternity. The most fascinating context the author argues about people can lose the ability to forget everything that is captured, but people are not able to not treasure the moments like nothing. To selective forgetting, I think there is memory storage of space we should selectively try retrieve a specific memorable moment particular as possible to recollected the portraits. Many people had a social network condition problem, since the 21st century cultural now places people on the media way too often. Then the invention of the camera was invented, people all around the world had used digital photographs to capture momentous occasion with a simple click of a button. As technology had been advantage rapidly, we were able to take most of the moments on videos, on disc, and even on our smart phones. Instagram was another attractive popular trending media specifically for teenagers, and the media was encounter exclusively for â€Å"photo-sharing services.† Basically, people were exposed to the internet too many, where they had forgot about narcissism.Show MoreRelatedEssay on Literary Insperation of the Holocaust1664 Words   |  7 PagesLiterary Insperation of the Holocaust Why do the survivors of such a tragic event such as the Holocaust want to remember those horrifying times by writing about memories that most people would only want to forget? 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